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Junction Isolation in Germanium by Alloy Process

IP.com Disclosure Number: IPCOM000092490D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gansauge, P: AUTHOR

Abstract

This technique provides device isolation in germanium by a low-temperature alloying process. In this way, impurity distribution in an epitaxial layer and in previously diffused transistors or diodes is not affected. N-type epitaxial layer 1 is deposited on a P-type substrate 2, orientation <001>, and contains NPN transistors 3 already diffused in layer 1. Aluminum stripes 4 are then deposited on layer 1 aligned parallel to 111 marks. Stripes 4 are alloyed into layer 1 by heating up to 600o C for several minutes. The alloy fronts are limited by 1 1 1 planes 5. In this manner, wedge-shaped P-regions 6 are formed which divide epitaxial layer 1 into electrically isolated N-type islands 7.

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Junction Isolation in Germanium by Alloy Process

This technique provides device isolation in germanium by a low-temperature alloying process. In this way, impurity distribution in an epitaxial layer and in previously diffused transistors or diodes is not affected. N-type epitaxial layer 1 is deposited on a P-type substrate 2, orientation <001>, and contains NPN transistors 3 already diffused in layer 1. Aluminum stripes 4 are then deposited on layer 1 aligned parallel to 111 marks. Stripes 4 are alloyed into layer 1 by heating up to 600o C for several minutes. The alloy fronts are limited by 1 1 1 planes 5. In this manner, wedge-shaped P-regions 6 are formed which divide epitaxial layer 1 into electrically isolated N-type islands 7.

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