Browse Prior Art Database

Storage Cell

IP.com Disclosure Number: IPCOM000092493D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gardner, PAE: AUTHOR [+2]

Abstract

Information is stored in the storage cell of drawing 1 by appropriate energization of the word and bit lines. When storing a 1, transistor 1 is conducting and transistor 2 is cut off. When storing a 0, transistor 2 is conducting and transistor 1 is cut off. The cell is interrogated by applying an interrogation pulse to the word line which appears on the bit-sense line connected to the conducting transistor.

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Storage Cell

Information is stored in the storage cell of drawing 1 by appropriate energization of the word and bit lines. When storing a 1, transistor 1 is conducting and transistor 2 is cut off. When storing a 0, transistor 2 is conducting and transistor 1 is cut off. The cell is interrogated by applying an interrogation pulse to the word line which appears on the bit-sense line connected to the conducting transistor.

A matrix of such cells behaves as a resistor matrix, the resistors being the collector load resistors 3 of the cells. As such, the magnitude of the signal appearing on a particular bit-sense line depends upon the number of additional conducting transistors connected to that bit-sense line. As such, the magnitude of the sense signal is information dependent and consequently leads to tolerancing problems with the detecting device connected to the line.

Drawing 2 shows an arrangement which avoids this situation. Each cell is provided with a constant current source which takes the place of the collector load resistors. The constant current source is constructed of two field effect transistors 4. The latter are either function or insulated gate types which are supplied from voltage line 5. The cell is interrogated by pulsing the word line which modulates the amplitude of the current source.

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