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Metal Oxide Transistor Decode Circuit

IP.com Disclosure Number: IPCOM000092494D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Moore, RL: AUTHOR [+2]

Abstract

The decoder receives logic variable inputs and produces outputs that are a preselected function of the state of the inputs. In the example, the four inputs receive logic variables A and B and their complements. The output terminals represent different logic functions of the inputs. The circuit uses metal oxide semiconductor MOS transistors, represented by squares.

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Metal Oxide Transistor Decode Circuit

The decoder receives logic variable inputs and produces outputs that are a preselected function of the state of the inputs. In the example, the four inputs receive logic variables A and B and their complements. The output terminals represent different logic functions of the inputs. The circuit uses metal oxide semiconductor MOS transistors, represented by squares.

The input and output lines are arranged in a matrix so that each input line crosses every output line. MOS transistors are located at selected intersections of the matrix. Each transistor has its gate terminal connected to one input line. The drain and source terminals of each transistor are connected in one of the output lines. Thus the transistors control conduction in the output lines in response to the input signals. The series connection of two transistors forms an And function of the input signals. For example, the right-hand most output line includes in series an MOS transistor that is turned on in response to logical variable A and an MOS transistor that is turned on in response to logical variable
B. Thus the output of this line represents the logic function AB.

Preferably the decoder is an integrated circuit structure. It includes a silicon substrate. The pattern of MOS transistors is formed by suitably diffusing impurities into the substrate at selected points. The input and output wires are then formed in two metalized layers.

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