Browse Prior Art Database

Memory Protection System

IP.com Disclosure Number: IPCOM000092507D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 60K

Publishing Venue

IBM

Related People

Shattuck, DC: AUTHOR [+2]

Abstract

In data processing machines with magnetic core or similar memories, especially stored program data processing machines, it is desirable that information in memory be protected from loss or change when power to the machine is lost or fluctuates greatly. The arrangement grounds the input to the memory driver after a read-write cycle is terminated to thus protect the memory from further action upon it. Restart is under keyboard control by the machine operator.

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Memory Protection System

In data processing machines with magnetic core or similar memories, especially stored program data processing machines, it is desirable that information in memory be protected from loss or change when power to the machine is lost or fluctuates greatly. The arrangement grounds the input to the memory driver after a read-write cycle is terminated to thus protect the memory from further action upon it. Restart is under keyboard control by the machine operator.

Drawing 1 shows the circuitry to monitor the DC power supply of the data processing system and to create a relatively high-voltage signal when DC power is above a certain level. DC detector A is connected to integrator B which, in turn, is connected to isolating Inverter C. Integrator B provides a delay so that a power on signal is not recognized when a power level is just starting to build up. Integrator B also smooths variations detected so that the output does not respond to momentary level shifts which are not significant. Inverter C isolates and inverts the signal presented to it by integrator B.

In detector A, when DC power is at a normal level, zener diode D7 passes current sufficient to turn transistor T9 on. When T9 is on, transistors T11 and T13 are held off. When DC power drops such that D7 resists current flow, T9 is turned off. This forces T11 and T13 on, and the current to transistor T11 is amplified so as to supply a quite large current to T13.

Thus, when the voltage drops a sufficient amount so that conduction across D7 is blocked, T13 is heavily biased to conduction. This tends to discharge quite quickly capacitor C15 in integrator B, since resistor R17 is of relatively small magnitude. When power is regained after having been lost, charging is through resistor R19 which is of much larger magnitude. A much longer time delay, about one second, occurs before C15 is charged to a sufficient magnitude to turn transistor T21 on. The time delay during increase in voltage gives the power supply time to come to a definite high level. A high level of DC power ultimately creates a high voltage on output 23. A low level ultimately brings output 23 to substantially ground potential.

Drawing 2 shows a latch which creates the actual signal used to protect memory from access after a write cycle when DC power is lost. Drawing 2 is illustrative. That is, it does not show diodes and specific circuit elements of the latch. The amplifier and inverter transistor T30 serves to amplify and invert signals to it. Amplifier 32 provides further gain and inverts the signal received from T30.

Output 44 of amplifier 32 is connected to the input at terminals 34 and 36. The connections shown are such that a change in status created by concurrent signals at the input is held. Thus, if all signals on one of legs 38, 40, and 42 are up, the leg is satisfied and the T30 is driven on. With T30 on, a potential of substantially ground appears as the input to amplifier 32. A re...