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Control Memory Storage Cell

IP.com Disclosure Number: IPCOM000092508D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Pleshko, P: AUTHOR

Abstract

This bit storage cell, especially suitable for use in control memories, requires only three field effect transistors, one word line, one common bit-sense line, and a pair of resistors.

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Control Memory Storage Cell

This bit storage cell, especially suitable for use in control memories, requires only three field effect transistors, one word line, one common bit-sense line, and a pair of resistors.

Field effect transistors T1 and T2 are arranged in a flip-flop circuit, with the source electrode of T1 grounded and the source electrode of T2 connected to a common bit-sense line CBSL of the memory array. The drain electrodes of T1 and T2, respectively, are cross-coupled to each others' gate electrodes. A third field effect transistor T3 is arranged with its source and drain electrodes connected respectively between the drain electrodes of T1 and T2. The gate electrode of T3 is connected to a word line WL of the memory array.

To write information into the cell, lines WL and CBSL are simultaneously pulsed. For writing 0, both of these lines are pulsed positively, causing T1 to be rendered conductive and T2 nonconductive. For writing 1, WL is pulsed positively and CBSL negatively, causing T2 to be rendered conductive and T1 nonconductive.

To read the stored information, WL is pulsed positively, thus effectively connecting drain resistors R1 and R2 in parallel. If the cell is storing 1, T2 conducting, this action raises the potential of CBSL and thus produces a positive- going sense signal on that line. If the cell is storing 0, T1 conducting, there is substantially no change in the potential of CBSL during readout.

The advantages of this cell are that it...