Browse Prior Art Database

Block Resetting of a Monolithic Integrated Semiconductor Circuit

IP.com Disclosure Number: IPCOM000092510D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Agusta, BA: AUTHOR [+2]

Abstract

This block resetting technique is applicable for monolithic integrated semiconductor circuits of the latch type.

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Block Resetting of a Monolithic Integrated Semiconductor Circuit

This block resetting technique is applicable for monolithic integrated semiconductor circuits of the latch type.

In drawing A, an integrated monolithic semiconductor structure generally designated 1 has a pair of P-type resistors 2 and 3 located in N-type region 4. The latter is reverse biased by lead 5 which is connected to positive potential VC.

Isolation of region 4 is achieved by P-type region 6 surrounding N region 4. Region 6 is connected by lead 7 to ground potential. Areas 8 and 9 represent NPN transistor structures, each of which is junction-isolated by region 6. Transistors 8 and 9 are part of a latch circuit not shown.

In drawing C, voltage V is applied to resistors 2 and 3 to achieve cutoff of the latch. Resistors 2 and 3 have different resistance values. Such assures that upon application of V, which is above the cutoff potential, that the latch becomes set at a fixed conductive state.

In drawing B, and AC reset signal applied through capacitor 10 also serves to set the latch at a fixed conductive state. Resistance 12 depicts the resistance of the monolithic integrated substrate.

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