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Pulse Width Code Normalization

IP.com Disclosure Number: IPCOM000092551D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Cutaia, A: AUTHOR

Abstract

The system normalizes decoding apparatus in pulse-width code detectors. In some data processing systems the pulse-width code can have a large tolerance. However, for a string of pulse-width code message blocks the assigned width of pulses can vary only slightly. Therefore it is desirable to normalize a pulse-width code detector to the relative size of pulses during a string of message blocks.

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Pulse Width Code Normalization

The system normalizes decoding apparatus in pulse-width code detectors. In some data processing systems the pulse-width code can have a large tolerance. However, for a string of pulse-width code message blocks the assigned width of pulses can vary only slightly. Therefore it is desirable to normalize a pulse-width code detector to the relative size of pulses during a string of message blocks.

In operation, pulses are decoded by counting the number of clock pulses occurring during the duration of a pulse. The pulse-width code is applied on line 10 to And's 12 and 14. When a pulse is present on line 10, clock pulses are passed by And 12 to counter 16. When a pulse is not present on line 10, the clock pulses are passed through And 14 to counter 18. Thus, the count in counter 16 is a measure of the duration of pulses. The count in counter 18 is a measure of the duration of time since the last pulse.

In normal operation, counter 16 starts at a 0 count and counts clock pulses during the duration of a pulse on line 10. The duration or pulse width is decoded by And's 20, 22 and 24. These are activated by a signal from And 26. The latter generates a signal when counter 18 exceeds a given count. In effect the output of And 26 indicates the end of the pulse being decoded.

When the end of pulse signal from And 26 activates And's 20, 22 and 24, only one of them has an output signal. And 20 is looking for a greater than 35 count. And 22 is looking for a count of 20 +/- 3. And 24 is looking for a count of 10 +/- 3. An output from And 24 indicates that the pulse on line 10 is a 0 bit. An output from And 22 indicates that the pulse on line 10 is a 1 bit.

Finally, an output from And 20 indicates that the pulse is a start or end of message pulse. The start or end of message pulse is referred to as a D pulse.

The first D pulse in a message block sets trigger 28. The latter then gates on And 30. This passes the bits from And's 22 and 24 into parity check logic system
32. Trigger 28 is turned off by the next D pulse, i.e., end of message.

To reset counters 16 and 18 for the next pulse, Or 34 monitors the out...