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Instruction Branch by Stored Amount

IP.com Disclosure Number: IPCOM000092553D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Heard, RS: AUTHOR

Abstract

The upper drawing shows an instruction word. The bottom drawing shows the functions of a stored program machine in response to that instruction word. This implements a data processing technique which permits an efficient branching of instruction by a count stored in the instruction. Under the control of the instruction word, a bit in memory is sensed to determine if a branch is to be taken. If the branch is taken, then during the same machine cycle an arithmetic operation between the existing instruction address and a quantity from the instruction word is performed.

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Instruction Branch by Stored Amount

The upper drawing shows an instruction word. The bottom drawing shows the functions of a stored program machine in response to that instruction word. This implements a data processing technique which permits an efficient branching of instruction by a count stored in the instruction. Under the control of the instruction word, a bit in memory is sensed to determine if a branch is to be taken. If the branch is taken, then during the same machine cycle an arithmetic operation between the existing instruction address and a quantity from the instruction word is performed.

The machine is a stored program machine in which all instruction words are stored in magnetic core memory and read out and operated upon in a sequence controlled by the machine. All instruction words have sixteen bit positions. Each bit position is of either 1 or 0 significance. The bit positions are numbered 1...16.

In the instruction word, bits 1 and 12...16 are control codes which are read into latches which control an entire cycle of machine operation. Bit 12 defines whether a branch of instruction is to be executed when a sensed bit is a 1 rather than 0. Bit 14 defines whether the increment taken is to be additive or subtractive. The other of bits 1 and 12...16 define that the general steps of incremental jump, as described occur.

Bits 6...11 are bits which designate the location of the data bit in memory, one bit in a designated sixteen bit register, which is to be interrogated. Thus, bits 6 and 7 are capable of four permutations and are used as an address to locate one of four preselected registers. Bits 8...11 are capable of sixteen permutations and are used as an address to locate a specific one of the sixteen bits in the addressed register. With regard to the lower drawing, the address of the next instruction in the machine sequence is always stored in the Instruction Address Memory IAM. The latter is associated with structure which permits it to be addressed without reference to a register containing an address for it. A clock creates signals which are the machine processing times. At time T1 the machine automatically brings the instruction address from IAM to the Address Control Register ACR. At this time the data processing machine is not structured to in any way recognize that the address moved from IAM to ACR is that of an incremental jump instruction as described. During T1 the contents of IAM are increased by the normal amount, which can be one or two depending upon the machine, and restored in IAM since this address is the one to be used next if a branch does not occur.

During T2 the machine automatically interrogates the sixteen bits magnetic memory M designated by ACR. These sixteen bits are the instruction. The instruction is written back into the same register for use in subsequent operations and is written into Access Register AR. The latter is also associated with structure which permits all or...