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Overlapping Operands of a Translate Instruction

IP.com Disclosure Number: IPCOM000092554D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Adler, LG: AUTHOR [+2]

Abstract

A translate instruction in a data processing system uses the data in a byte of an operand as an address of a byte in a table and replaces the data byte by the table byte. When the bytes of an operand are all replaced, the new operand can be stored and a second operand word fetched from storage for translation. In this machine, it is possible that a byte of the translated part of the word being processed can be called for as a table byte before the word is placed into storage.

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Overlapping Operands of a Translate Instruction

A translate instruction in a data processing system uses the data in a byte of an operand as an address of a byte in a table and replaces the data byte by the table byte. When the bytes of an operand are all replaced, the new operand can be stored and a second operand word fetched from storage for translation. In this machine, it is possible that a byte of the translated part of the word being processed can be called for as a table byte before the word is placed into storage.

The I unit 1 initially decodes a translate instruction and instructs the main storage control element MC 2 to fetch the first argument word from main store 3 and to send it to operand register 4. At the same time it instructs MC 2 to store the processed operand back into the main store address from which it was fetched. This is done by putting the address into storage address register SR5 in MC
2. I Unit 1 sets the address of the first operand byte to be processed into byte address counter BC 6 associated with register 4. The set BC 6 then gates out on bus 7 the operand byte, addressed by BC 6, to I Unit 1 which uses it to prepare the address of the first table byte. The full word part of the prepared address is sent to MC 2 to fetch the word to A register 8. The byte designating part of the address is sent to BC 6 associated with register 8. Then BC 6 is incremented by a unit and the addressed second operand byte is sent to I Unit 1 to generate a second address for a table word to...