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Maintaining Sequences of Randomly Assigned Buffers

IP.com Disclosure Number: IPCOM000092561D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Calta, SA: AUTHOR [+2]

Abstract

When a plurality of data words is to be transferred between an I/O device control channel having one operating speed and a data store having a different operating speed, a substantial saving of the time normally required for switching operations can be made. Such is realized if a plurality of the data words made available at the operating speed of the supplying unit are first stacked in buffer registers and are then continuously dumped into the receiving device at its operating speed. This arrangement sets up a sequence of buffer registers for each channel of a data processor. Each channel has a first entry register 1 and a last entry register 2. One indicates the buffer register containing the first data word of the stored sequence. The other contains the address of the buffer register storing the last word of the sequence.

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Maintaining Sequences of Randomly Assigned Buffers

When a plurality of data words is to be transferred between an I/O device control channel having one operating speed and a data store having a different operating speed, a substantial saving of the time normally required for switching operations can be made. Such is realized if a plurality of the data words made available at the operating speed of the supplying unit are first stacked in buffer registers and are then continuously dumped into the receiving device at its operating speed. This arrangement sets up a sequence of buffer registers for each channel of a data processor. Each channel has a first entry register 1 and a last entry register 2. One indicates the buffer register containing the first data word of the stored sequence. The other contains the address of the buffer register storing the last word of the sequence.

Each channel also has a set of control triggers 3 including a buffer counter 4. The latter is incremented each time a channel data word, either to or from the channel, is put into a buffer register. Counter 4 is decremented each time a channel data word is removed from a buffer register. Each buffer register has associated with it an address register 5 to contain the address of the next buffer in the sequence of which it is a part. A common channel current buffer address register 6 contains the address of the next buffer to be stored into. The common storage current buffer address register 7 contains the address of the next buffer register to be read from.

Assume that the first word of a sequence is received from one of the channels, the channel current buffer address in register 6 is transmitted to register 2 for the channel. Since this is the first entry of the sequence, counter 4 equals 0, the address is also entered into the channel's register 1. The data word itself goes into the buffer register identified by the address in register 6. Counter 4 is...