Browse Prior Art Database

High Resolution Timer

IP.com Disclosure Number: IPCOM000092563D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Gilgoff, JL: AUTHOR [+2]

Abstract

An interval timer for a processor which has minimum requirements for storage referencing is provided by storing the high-order bytes of the timer in main storage. A hardware register and logic supplies the low-order timer byte. Logic circuitry permits the processor to ignore one or more requests from the hardware logic to update the high-order bytes in the storage without loss of timer data.

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High Resolution Timer

An interval timer for a processor which has minimum requirements for storage referencing is provided by storing the high-order bytes of the timer in main storage. A hardware register and logic supplies the low-order timer byte. Logic circuitry permits the processor to ignore one or more requests from the hardware logic to update the high-order bytes in the storage without loss of timer data.

A word representing the timer interval is entered under program control from processor logic 10 with the high-order bytes being placed in main store 11. The low-order byte or bytes are placed in register 12. Timing pulse generator 15 produces periodic pulses which cause 12 to be decremented by decrement circuit 13 through gate 14 and, after delay 16, gate the contents of 12 into register latches 20 through gate 18. Since 10 and 15 operate asynchronously, circuits 12, 13, and 20 must be of sufficiently fast response to be compatible with high-speed operation of 10 while also functioning with the relatively low-speed operation of 15. Otherwise 15 could directly decrement 12.

Whenever 12 is decremented to all zeros, decoder 21 conditions And 22 which in conjunction with the output of 16 sets latch 24. Delay 23 prevents conditioning of And 25 and thus the setting of buffer latch 26 and conditioning of And 27 until the output of 15 deconditions 27. Setting of 24 indicates to 10 that a microprogram routine is needed to update the interval timer count stored in 11. Performance of the update routine by 10 results in a signal on line 33 w...