Browse Prior Art Database

Error Control for Buffer Registers

IP.com Disclosure Number: IPCOM000092564D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Granito, GD: AUTHOR [+2]

Abstract

In large data processors, extensive buffering is normally provided between I/O units and data storage units to adjust data flow rates and provide a smooth now of data. Any breakdown in structure of such buffering devices can force shutdown of most, if not all, of such a large system. In this structure, faulty buffers can be eliminated from use without effect on other buffers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Error Control for Buffer Registers

In large data processors, extensive buffering is normally provided between I/O units and data storage units to adjust data flow rates and provide a smooth now of data. Any breakdown in structure of such buffering devices can force shutdown of most, if not all, of such a large system. In this structure, faulty buffers can be eliminated from use without effect on other buffers.

A plurality of I/O Channels 1 can transmit data and requests to a set of buffer registers 2, over bus 3, and through ingate controls 4. Normally, controls 4 transfer the information on bus 3 to any available buffer register 3. In a similar manner, any one of a plurality of stores 5 can transmit requested data over bus 6 to controls 4 for distribution to registers 2. On the other side of registers 2, outgate control 7 distributes the data from registers 2 over bus 8 to stores 5, or over bus 9 to channels 1. In such a system, if an error occurs, it is often desirable to retain in the register 2 the data of the instruction in which the error occurred until the data can be inspected by a maintenance engineer or recorded in a logging out operation. Each register 2 has associated with it a hold bit trigger 10. The latter, when set, prevents the assignment of its associated register 2 to an incoming signal and, in effect, retains in the register 2 the data which it had when trigger 10 was set. These triggers 10 can be individually set by error detection controls 1...