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Browse Prior Art Database

Capacitive Card Read Only Memory

IP.com Disclosure Number: IPCOM000092568D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Sproul, WW: AUTHOR

Abstract

The capacitive card read-only memory comprises bit card 10 superposed on word card 20. Card 10 comprises dielectric substrate 11 having one or more parallel bit lines B1...B3 on its upper surface. Each bit line has plural integral bit planes 12 uniformly spaced to provide a row of bit storage locations. Word card 20 comprises dielectric substrate 21 having parallel word lines 22 superimposed on the bottom surface of substrate 21. Each word line 22 which runs orthogonally to bit lines B1...B3 includes plural integral word plates 23. These are located below each plane 12 and in cooperation with them provide plural capacitive storage locations.

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Capacitive Card Read Only Memory

The capacitive card read-only memory comprises bit card 10 superposed on word card 20. Card 10 comprises dielectric substrate 11 having one or more parallel bit lines B1...B3 on its upper surface. Each bit line has plural integral bit planes 12 uniformly spaced to provide a row of bit storage locations. Word card 20 comprises dielectric substrate 21 having parallel word lines 22 superimposed on the bottom surface of substrate 21. Each word line 22 which runs orthogonally to bit lines B1...B3 includes plural integral word plates 23. These are located below each plane 12 and in cooperation with them provide plural capacitive storage locations.

For obtaining constant capacitive loading of the bit and word lines, ground plate 14 is provided at each bit position intermediate planes 12 on the upper surface of card 10 and plates 23 on the bottom surface of card 20. Plates 14 are preferably superposed on the bottom surface of substrate 11 and are coplanar and integrally connected with parallel bit wires 15 and 17 and ground wire 16. To achieve constant capacitive loading, wire 15 is connected in common with line B3 and wire 17 is connected in common with bit line B2, for example. Similarly, bit wire 18 is connected in common with line B1.

Other bit lines, not shown, are similarly connected with corresponding bit wires. A 0 is stored at a particular bit position by punching a hole 19 in card 10 to form a break in the connection between wire 15 and plate 14. This leaves plate 14 connected only with a wire 16. A 1 is stored at any bit position by punching a hole 25 in card 10 to break the connection of plate 14 and wire 16.

This leaves plate 14 connected with the wire 15.

Constant...