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A Modified Loop Free, Flow Through Multiplier

IP.com Disclosure Number: IPCOM000092577D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Riganati, JP: AUTHOR [+2]

Abstract

The multiply unit multiplies two thirty-six bit operands. The multiplier is first recoded two bits at a time to yield nineteen operands. The function of the carry-save adder tree is to perform a nineteen fold weighted addition of the multiplicand.

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A Modified Loop Free, Flow Through Multiplier

The multiply unit multiplies two thirty-six bit operands. The multiplier is first recoded two bits at a time to yield nineteen operands. The function of the carry- save adder tree is to perform a nineteen fold weighted addition of the multiplicand.

Drawing A shows the general configuration and timing. Unit A accepts the input and is time multiplexed. Additional data is entered into the functional storage unit B. The terminology functional storage implies that while the unit is operating on the summands, its inherent delay is used as an integral part of the over-all process. The further processing by units C and D allows the intermediate results of D0 and D1 to be kept separated. Finally, unit E accepts the simultaneously available outputs of C and D and completes the processing.

Drawing B illustrates the flow for a typical 19 to 2 processor. Drawing C expands the carry-save adder CSA units.

The input gating and recoding logic of the system is considerably reduced over simple flow-through multiply systems. This is because it can be multiplexed, decoding multiplier positions 1...8 first and then positions 9...19.

The low-order multiplier positions 1...11 and the high-order multiplier positions 12...19 are processed separately, thus eliminating unnecessary overlap and minimizing CSA lengths compared to feedback multiply systems. The loop back-gating problems are also eliminated.

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