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Two Core Per Bit Memory

IP.com Disclosure Number: IPCOM000092596D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Brosseau, EF: AUTHOR

Abstract

Some ferrite core memories use two cores for each bit position. The drawing shows a two-core unit in which the cores have different heights. This construction provides an improved electrical output without the careful matching of core characteristics that is usually required for two-core per bit memories. In addition, this memory is adaptable to a simplified construction technique. The hysteresis loops that the two cores operate on are shown. Core A has a higher loop associated with its greater physical height. Each core has a clear position on its major hysteresis loop that is achieved during a clear operation before new data is written into the unit. Each core has a second operating point that is used for storing a 1 or a 0.

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Two Core Per Bit Memory

Some ferrite core memories use two cores for each bit position. The drawing shows a two-core unit in which the cores have different heights. This construction provides an improved electrical output without the careful matching of core characteristics that is usually required for two-core per bit memories. In addition, this memory is adaptable to a simplified construction technique. The hysteresis loops that the two cores operate on are shown. Core A has a higher loop associated with its greater physical height. Each core has a clear position on its major hysteresis loop that is achieved during a clear operation before new data is written into the unit. Each core has a second operating point that is used for storing a 1 or a 0. To write a 1, core A is magnetized to its 1 signifying point and core B is left in its clear position. To write a 0, core B is magnetized to its 0 signifying point and core A is left in its clear position. A word driver is turned on in cooperation with a 1 or a 0 bit driver to establish the selected storage state.

For a read operation, the two cores are energized by the word driver to operate along small, closed minor hysteresis loops. Both cores produce voltage signals on the associated bit lines. The voltages are detected by a differential sense amplifier. The core operating at the 1 or 0 storage position produces a significantly larger output than the core operating at the clear position. The output of the differential sense amplifier is a positive signal when a previously stored 1 is read. It is a negative signal when a previously stored 0 is read.

Because the word line is capacitively coupled to the bit lines, the read current in the word line produces appreciable noise on the two bit...