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High Capacitance PN Junction Capacitors by Etch Refill Method

IP.com Disclosure Number: IPCOM000092622D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Doo, VY: AUTHOR

Abstract

The capacitance of a capacitor is linearly proportional to the junction area. The capacitance per unit area is a function of dopant concentration in the junction area and C alpha (qN)/1/2/ = (T/micron)/1/2/ for an abrupt junction where C = capacitance per unit area, q = electronic charge, N = net donor concentration, Tau =electron conductivity, and micron=electron mobility. Diffused junctions usually have relatively graded dopant distribution, thus have relatively low capacitance per unit area. Epitaxially deposited junctions can be made very sharp, so that a large capacitance per unit area can be achieved.

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High Capacitance PN Junction Capacitors by Etch Refill Method

The capacitance of a capacitor is linearly proportional to the junction area. The capacitance per unit area is a function of dopant concentration in the junction area and C alpha (qN)/1/2/ = (T/micron)/1/2/ for an abrupt junction where C = capacitance per unit area, q = electronic charge, N = net donor concentration, Tau =electron conductivity, and micron=electron mobility. Diffused junctions usually have relatively graded dopant distribution, thus have relatively low capacitance per unit area. Epitaxially deposited junctions can be made very sharp, so that a large capacitance per unit area can be achieved.

A typical procedure for forming high capacitance PN junction capacitors starts with an N-type monocrystalline silicon wafer 1 having a silicon dioxide layer or film 2 grown or formed on the surface of wafer 1 as in drawing A. Opening 3, as in drawing B, is formed by etching using conventional photolithographic masking and etching techniques.

The exposed portion of wafer 1 is etched away using a suitable aqueous acid etching solution or a vapor etching solution to produce opening 4 in wafer 1 as in drawing C. P+ and then N+ monocrystalline silicon layers 5 and 6, respectively, are epitaxially grown in opening 4 of the wafer 1, as in drawing D. Drawing E shows the completed capacitor device with layer 2 etched away by conventional techniques.

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