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Monolithic Integrated Semiconductor Structure With Multilevel Conductive Interconnection Planes

IP.com Disclosure Number: IPCOM000092641D
Original Publication Date: 1966-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Agusta, BA: AUTHOR [+2]

Abstract

This is an improved monolithic integrated semiconductor structure with multilevel conductive interconnection planes which uses dielectric isolation for electrically isolating monocrystalline semiconductor regions.

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Monolithic Integrated Semiconductor Structure With Multilevel Conductive Interconnection Planes

This is an improved monolithic integrated semiconductor structure with multilevel conductive interconnection planes which uses dielectric isolation for electrically isolating monocrystalline semiconductor regions.

In drawing A, isolated monocrystalline semiconductor regions 1 are surrounded by bottom and side insulating layer 2 and by top insulating layer 3. Diffused regions and ohmic contacts to them are formed in each region 1 by conventional techniques. In order to provide an improved electrical underpass arrangement. metal surface lands 4 and 5 are electrically interconnected by underpass metal land 6. The latter is located between layer 2 and insulating layer 7. Substrate layer 8, preferably of polycrystalline material, is formed by conventional deposition techniques. Conductors 9 and 10 are permitted to extend on the surface of layer 3 normal to conductors 4 and 5 because of land 6.

In drawing B, the same reference numerals with the addition of letter A depict the corresponding regions in drawing A. In addition, metal land 12, which is electrically connected to conductive land 4A serves, together with metal land 14 which is electrically connected to conductive land 5A, to form a capacitor. Insulating layer 7A serves as the dielectric material between conductive lands 12 and 14. Insulator 16 serves to electrically isolate land 14 from substrate or polycrystalline...