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An Addressing System for Boundary Crossing

IP.com Disclosure Number: IPCOM000092701D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

McGovern, W: AUTHOR [+2]

Abstract

Storage is split into two halves 1 and 2, associated respectively with storage address registers Sar's 1 and 2. Each half stores a half-word and the output of storage with each reference is a full-word. When it is required to address a location at a half-word boundary, it is necessary to address one half-word with Sar 2 and the other with Sar 1, the address of the other one being N higher than that of the first half-word. With such a reference, the word read out of storage has portions taken from each half of storage.

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An Addressing System for Boundary Crossing

Storage is split into two halves 1 and 2, associated respectively with storage address registers Sar's 1 and 2. Each half stores a half-word and the output of storage with each reference is a full-word. When it is required to address a location at a half-word boundary, it is necessary to address one half-word with Sar 2 and the other with Sar 1, the address of the other one being N higher than that of the first half-word. With such a reference, the word read out of storage has portions taken from each half of storage.

To accomplish the readout from both halves by use of the address at the half- word boundary, such address is set from the Address Register into Sar 2. The address is also fed to +N circuitry 3 and to Exclusive-Or 4. Circuitry 3 performs a binary half-sum carry function and it generates those carries that, when Exclusive-Or'ed with the initial address, produce an address N higher than the original address.

The Address Register has binary triggers. To update the Address Register requires that it be incremented by N. This is done by using the output of circuitry 3 to control the triggers so that the original address and the output of circuit 3 are Exclusive-Or'ed by the triggers so as to increment the original address by N. Thus, the same hardware performs the dual functions of boundary crossing and address incrementing.

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