Browse Prior Art Database

Floating Point Data Flow

IP.com Disclosure Number: IPCOM000092703D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Ross, RD: AUTHOR

Abstract

In floating point arithmetic, the fraction arithmetic is performed in the basic arithmetic and logic section ALU of the CPU. A separate section of data flow is provided for characteristic or exponent arithmetic. This additional section of the data flow is logically equivalent to a corresponding section of the main arithmetic section of the ALU. In the latter, exponent registers 1 and 2 and a carry lookahead CLA perform the same logical functions on input data as corresponding registers in the ALU.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Floating Point Data Flow

In floating point arithmetic, the fraction arithmetic is performed in the basic arithmetic and logic section ALU of the CPU. A separate section of data flow is provided for characteristic or exponent arithmetic. This additional section of the data flow is logically equivalent to a corresponding section of the main arithmetic section of the ALU. In the latter, exponent registers 1 and 2 and a carry lookahead CLA perform the same logical functions on input data as corresponding registers in the ALU.

Floating point operands are stored in four floating point registers FPR 0, 2, 4, and 6. Each FPR can contain long precision, double word, floating point operands. Each FPR is split into two sections for handling high-order and low-order bits. The high-order section of used. For long precision operands both sections are used. This permits the high-order half of a FPR with the exponent and sign to be immediately available in hardware. Thus the control logic decisions connected with the exponent and sign can be determined sooner and simultaneously with the storage fetch of the low-order halves of the FPR's. The FPR's are connected to receive data from the ALU result register. A scratch register is also provided which receives data from an extension of the ALU result register. The scratch register is used to store parts of intermediate fraction results during floating point multiply or divide operations.

The FPR's and scratch registers are gated into the CPU data flow in the same manner as the GPR's. The high-order bits, exponent and sign, are also gated into two floating p...