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Exponential Waveform Generators

IP.com Disclosure Number: IPCOM000092716D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Mahoney, JP: AUTHOR [+2]

Abstract

The two circuits are exponential waveform generators which produce an output having a predetermined initial voltage, a predetermined final voltage, and a predetermined exponential time constant. The initial voltage, the final voltage, and the exponential time constant are adjustable in each circuit.

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Exponential Waveform Generators

The two circuits are exponential waveform generators which produce an output having a predetermined initial voltage, a predetermined final voltage, and a predetermined exponential time constant. The initial voltage, the final voltage, and the exponential time constant are adjustable in each circuit.

Circuit A is a positive wave shape generator. It has an independent RTCT time constant control employed in conjunction with a PNP transistor which controls the uplevel and downlevel of the output waveform. A conventional input switch and output driver are employed to, respectively, control the bias of the generator transistor and to isolate the low impedance output of the generator.

Circuit 13 is a negative exponential generator which includes a resistor- capacitor time constant control. The latter is connected in series between a downlevel source of potential and ground. There is a switching circuit comprised of a diode and a transistor. The clamping diode is normally biased to connect a capacitor to a second uplevel source of potential. The transistor switch is adapted to shunt the uplevel potential to reverse bias the diode and clamp the capacitor. The latter discharges to the downlevel potential, thus providing a corresponding waveform output for the generator. As in circuit A, a conventional output driver is employed to isolate the low-impedance output of the generator.

In circuit A, with the input stimulus pulse at a downlevel state, transistors T1 and T2 are biased off. The voltage at point A, v(1), is controlled by the Downlevel Control...