Browse Prior Art Database

Composite Division Unit

IP.com Disclosure Number: IPCOM000092745D
Original Publication Date: 1967-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Freiman, CV: AUTHOR [+2]

Abstract

The divider utilizes a table look-up 20 to provide a factor M. Such factor converts the divisor and the dividend such that the divisor is equal to 1 minus a very small number having a plurality of 0's, e.g., four zeros, after the decimal point. Table look-up 20 produces this factor M in factor register 30. Divisor register 10, register 30 and dividend register 40 are connected to factor multiplier 50 to produce such a divisor and dividend.

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Composite Division Unit

The divider utilizes a table look-up 20 to provide a factor
M. Such factor converts the divisor and the dividend such that the divisor is equal to 1 minus a very small number having a plurality of 0's, e.g., four zeros, after the decimal point. Table look-up 20 produces this factor M in factor register 30. Divisor register 10, register 30 and dividend register 40 are connected to factor multiplier 50 to produce such a divisor and dividend.

The quotient is provided in odd quotient register 130 and even quotient register 140. Since the first four bits of the small divisor number are zero, the first four bits of the dividend are applied to register 130. These first four bits of the dividend are multiplied in multiplier 170 by the small divisor number and since the small divisor number is negative are added in carry-save adder tree 80 to produce a first remainder in carry-save remainder registers 100 and 110.

The first four bits of the first remainder are assimilated in assimilator 120 and placed in register 140 so that they correspond to the 4th, 5th, 6th and 7th most significant bits of register 130. The first remainders in registers 100 and 110 are decoded by ternary decoder 160 and the first four bits are then multiplied by the small divisor number. A second remainder is obtained by way of multiplier 170, added in gates 60, buffer 70, and tree 80. The result in tree 80 is applied to the remainder registers 100 and 110. The third group of f...