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MOS FET Shift Register Element

IP.com Disclosure Number: IPCOM000092773D
Original Publication Date: 1967-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Short, RG: AUTHOR

Abstract

This shift register element has a minimum number of FET devices for the circuit function. The circuit operates at a clock frequency as high as 1 mHz.

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MOS FET Shift Register Element

This shift register element has a minimum number of FET devices for the circuit function. The circuit operates at a clock frequency as high as 1 mHz.

FET devices Q1...Q14 each include gate electrode 20, source electrode 22, and drain electrode 24. A device is in off condition when the voltage on electrode 20 is zero with respect to electrode 22. The device is in an on condition when electrode 20 is negative with respect to electrode 22. A 1 condition is represented in the circuit by an up level or 0 volt condition. A 0 condition is represented in the circuit by a down level or -10 volt condition.

A Data and Inverted Data signal are supplied as first inputs to Or's 32 and 34 respectively. Or's 32 and 34 provide a first input to Nand's 28 and 30 respectively. The combination functions as a first latch 26. Set 36 and reset 38 signals are supplied as second input signals to Nand's 30 and 28 respectively. The outputs of latch 26 are provided as first inputs to And's 40 and 42. The outputs of the latter and Nor's 46 and 48 function as a second latch 44. A true output 50 and an inverted output 52 are provided by latch 44.

Control input 54 is connected as a second input to Vie Or's and And's associated with latches 26 and 44 respectively. As input 54 is altered between an up or 1 condition and a down or 0 condition, information is transferred in the register element. Input 54 is normally up. To begin a shift, input 54 is lowered to enter data into the first latch. When input 54 is lowered, Q2 and Q8 are turned on and the condition of latch 26 is set so that the signal level at the Data Input and Inverted Data Input terminals appears at the outputs of Nand's Q5 and Q6, and Q3 and Q4, respectively. The Data Input and Inverter Data Input are not changed while input 54 is down.

The output from latch 26 is provided over lines 56 and 58 to the inputs o...