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Memory Core Test Head

IP.com Disclosure Number: IPCOM000092792D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Mayer, KL: AUTHOR [+2]

Abstract

The circuit is used in a tester of magnetic memory cores. This circuit delivers fast and clean current waveforms to the core and compensates for electrical pickup noises inherently generated infast circuits.

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Memory Core Test Head

The circuit is used in a tester of magnetic memory cores. This circuit delivers fast and clean current waveforms to the core and compensates for electrical pickup noises inherently generated infast circuits.

The circuit consists of a plurality of driver inputs 1, each with its own terminating resistor 2. Each input is reserved for one test pulse, allowing the resistor 2 to be selected so as to match the input transmission line impedance. The drive current in line 5 is monitored by current probe 3 and displayed by conventional devices.

Compensating loop 4 induces a voltage from drive line 5 into sense line 6. This voltage is opposite in phase to a voltage inductively induced into sense line 6 through core probe 7 with no core present.

Noise is also capacitively induced into line 6 through probe 7. This capacitive noise is smaller in magnitude and slightly earlier in time than the inductive noise. Delay line 8, in retarding the noise train from probe 7, insures that the compensating voltage cancels the composite noise voltage. The signal from the sense output is the true representation of a core behavior under the test conditions.

Although a split core probe is shown, the above principle s also solve noise problems in core testers with solid core probes.

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