Browse Prior Art Database

Circuit Plane Core Tacking

IP.com Disclosure Number: IPCOM000092795D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Solomon, JM: AUTHOR

Abstract

Multiple layers of insulative base material and conductive material for printed circuit manufacture are handled with improved efficiency by tacking each group of layers with soft metal rivets.

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Circuit Plane Core Tacking

Multiple layers of insulative base material and conductive material for printed circuit manufacture are handled with improved efficiency by tacking each group of layers with soft metal rivets.

During the exposure step for each laminated pair of base 1 and conductive 2 layers, layer 1 is punched in the margin with aligning holes 3 and tacking holes 4. Multiple layers are stacked on pins in holes 3 to form a core. Soft metallic rivets 5 are pressed and flared in holes 4 to hold the core layers in place. Rivets 5 are disks punched from flat, pure, high-melting point, 400 degrees F or above, lead, tin alloy or alloy of equivalent softness.

When assembled cores are to be laminated, they are laid up between planishing plates 6 and are strong enough to be aligned against a straight edge in the press. Lamination takes place without the necessity of providing holes in the planishing plates for aligning pins because the rivets are flush with the surface of the core plane and are easily deformed under the applied heat and pressure.

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