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Nontime Coincidence 2/D Memory Method

IP.com Disclosure Number: IPCOM000092797D
Original Publication Date: 1967-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Holzinger, CS: AUTHOR [+2]

Abstract

Ferrite cores can be operated in a 2-D memory without the necessity of using time coincidence between the bit and word-write pulses by taking advantage of the phenomenon shown in A and 13. After resetting a core to the remanence state R, a reverse polarity pulse of amplitude a switches more flux, point t', than does the application of a reverse polarity pulse of amplitude b, which is less than a, followed by a reverse polarity pulse of amplitude a, point t''. The application of many b pulses to a core in either state t' or state t'' sets in some additional amount of flux but does not appreciably change the flux state.

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Nontime Coincidence 2/D Memory Method

Ferrite cores can be operated in a 2-D memory without the necessity of using time coincidence between the bit and word-write pulses by taking advantage of the phenomenon shown in A and 13. After resetting a core to the remanence state R, a reverse polarity pulse of amplitude a switches more flux, point t', than does the application of a reverse polarity pulse of amplitude b, which is less than a, followed by a reverse polarity pulse of amplitude a, point t''. The application of many b pulses to a core in either state t' or state t'' sets in some additional amount of flux but does not appreciably change the flux state.

The pulse sequence for a 2-D nontime coincident memory mode is shown at
C. In this mode the binary 1 state is at t' and the binary 0 state is at t''. Cores can be also operated using this phenomenon in a two-core per bit memory as shown in D. If the pulse mode of C is employed in the D structure, a significant output is produced when a 0 is stored and no output. when a 1 is stored. The outputs can be reversed by applying a bit signal when a 1 is to be written rather than when a 0 is to be written in the two-core structure.

Since the pulses need not be time-coincident, this mode of operation is particularly useful in large capacity memories where array delays make timing an accute problem. The same modes can also be employed in performing time sequence logic.

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