Browse Prior Art Database

Decoded Decimal Counter

IP.com Disclosure Number: IPCOM000092844D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Miller, EW: AUTHOR [+2]

Abstract

This is a decoded decimal counter with the decoded output determining the next count. Two timings are associated with the counter. An A pulse and a B pulse alternate and are nonoverlapping. Initially, both registers I and register II contain one of the ten legitimate bit configurations shown in the following table: Decoder Reg. I, Reg.

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Decoded Decimal Counter

This is a decoded decimal counter with the decoded output determining the next count. Two timings are associated with the counter. An A pulse and a B pulse alternate and are nonoverlapping. Initially, both registers I and register II contain one of the ten legitimate bit configurations shown in the following table: Decoder

Reg. I, Reg. II Output

E D C B A

0 0 0 0 0 Zero

0 0 0 0 1 One

0 0 0 1 1 Two

0 0 1 1 1 Three

0 1 1 1 1 Four

1 1 1 1 1 Five

1 1 1 1 0 Six

1 1 1 0 0 Seven

1 1 0 0 0 Eight

1 0 0 0 0 Nine.

To increment the counter, the decoder output is combined in And's gating the A pulse to set or reset one of the five latches of register I to form the bit configuration of the next count. The contents of register I are transferred to register L via And's under control of the B pulse and the next sequential output is decoded in the decoder.

The decoder can, for example, be comprised of nine 2-legged And's coupled to the outputs of register L to provide ten decoded outputs as follows: Zero = A . E

One = A . B

Two = B . C

Three = C . D

Four = D . E

Five = A . E

Six = A . B

Seven = B . C

Eight = C . D

Nine = D . E.

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