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High Density Circuit Board

IP.com Disclosure Number: IPCOM000092845D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Haddad, MM: AUTHOR [+2]

Abstract

This process provides extremely small etched lines on the outer plane surface of a board adjacent plated through-hole connections. An internal plane board 11 is drilled with hole 13, catalyzed, coated with coating 15 and through-hole plated 17 to internal line 18. A hole 13 is then filled flush with a short pin 19. Coating 15 is screened on after catalyzing to prevent plating on the surface and then is removed to expose a pin 19. Cured insulating layer 21 having a copper clad 23 is laminated on board 11 using an adhesive. Photoresist 25 is applied and has a fine hole pattern 27 of the order of 5 to 8 mils diameter. Copper clad 23 is etched and then layer 21 is etched until a fine hole 31 reaches a pin 19. The last steps apply interconnection 29 by plating as follows by: 1. Cleaning holes by vapor blasting, 2.

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High Density Circuit Board

This process provides extremely small etched lines on the outer plane surface of a board adjacent plated through-hole connections. An internal plane board 11 is drilled with hole 13, catalyzed, coated with coating 15 and through-hole plated 17 to internal line 18. A hole 13 is then filled flush with a short pin
19. Coating 15 is screened on after catalyzing to prevent plating on the surface and then is removed to expose a pin 19. Cured insulating layer 21 having a copper clad 23 is laminated on board 11 using an adhesive. Photoresist 25 is applied and has a fine hole pattern 27 of the order of 5 to 8 mils diameter. Copper clad 23 is etched and then layer 21 is etched until a fine hole 31 reaches a pin 19. The last steps apply interconnection 29 by plating as follows by:
1. Cleaning holes by vapor blasting,
2. Sensitizing and catalyzing the holes for electroless plating,
3. Applying a dense negative circuit photoresist pattern,
4. Electroless copper plating,
5. Electroplate resist plating, and
6. Removing the photoresist and etch so that a fine hole 32

is left for module

connecting and so that printed circuit lines 33 are

closely spaced to a hole 32.

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