Browse Prior Art Database

Clock

IP.com Disclosure Number: IPCOM000092858D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR [+2]

Abstract

As the speed of logic circuits is increased to meet the demand for higher performance computers, the more complex the problem of clocking becomes. A five-stage clock ring is shown in A having stages B...F. This ring furnishes 5 to 75 nanosecond basic overlap pulses in a 250 nanosecond cycle time as shown in B. By Anding these five basic pulses, either 10 to 25 nanosecond pulses or 10 to 50 nanosecond pulses can be obtained. Oring of the five basic pulses results in pulses of longer duration.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Clock

As the speed of logic circuits is increased to meet the demand for higher performance computers, the more complex the problem of clocking becomes. A five-stage clock ring is shown in A having stages B...F. This ring furnishes 5 to 75 nanosecond basic overlap pulses in a 250 nanosecond cycle time as shown in B. By Anding these five basic pulses, either 10 to 25 nanosecond pulses or 10 to 50 nanosecond pulses can be obtained. Oring of the five basic pulses results in pulses of longer duration.

The clock circuit in A can be packaged on a single integrated module unit. This packaging of the basic clock ring on a single module helps minimize the clock skew and distribution problems. This basic clock module is then placed on small cards throughout the system where clocking is required. The output of the basic clock modules is restricted as to loading and net length.

There is still one basic oscillator in the entire processing unit. However, distribution of the oscillator output to each clock module is accomplished by selection of the proper delay line taps in a delay line. Thus each clock module within a system sees the oscillator pulse precisely at the same time. Selection of the oscillator delay line tap also provides unique clocking offset arrangement so that the clock pulses of a given clock module can be offset from any other clock module pulses.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]