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Fast Registers

IP.com Disclosure Number: IPCOM000092862D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR [+3]

Abstract

Registers B and C have a plurality of bit positions, typical ones of which are shown. The registers are arranged so that a first bit is placed in both registers and then a second bit is placed in both registers so as to be Exclusive-Or'ed with the first bits in them. The associated register bit positions have flip latches FLB and FLC whose output lines are complemented and provide signals representing the bits stored in them. And's A1, A2, A5, and A6 are connected through an Or to the set side of FLB and FLC respectively. And's A3, A4, A7, and A8 are connected through an Or to the reset side of FLB and FLC respectively. Each A1...A4, A5, and A7 requires a DC conditioning signal and a voltage change set signal to produce an output.

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Fast Registers

Registers B and C have a plurality of bit positions, typical ones of which are shown. The registers are arranged so that a first bit is placed in both registers and then a second bit is placed in both registers so as to be Exclusive-Or'ed with the first bits in them. The associated register bit positions have flip latches FLB and FLC whose output lines are complemented and provide signals representing the bits stored in them. And's A1, A2, A5, and A6 are connected through an Or to the set side of FLB and FLC respectively. And's A3, A4, A7, and A8 are connected through an Or to the reset side of FLB and FLC respectively. Each A1...A4, A5, and A7 requires a DC conditioning signal and a voltage change set signal to produce an output. It is necessary to apply the conditioning signal a short time period T ahead of the set signal. A6 and A8 require the coincidence of two similar voltage levels to provide an output signal.

In operation, conditioning signal Bit 1 is applied to A2, and shortly afterward a Set B Reg set signal is applied to A2 causing FLB to be set after a time lapse T1 due to circuit delays. A Set B into C signal is applied to And's A6 and A8 so that when the B Reg bit output signals are also applied to these And's, the necessary coincident signal sets FLC to represent a C bit in accordance with the B Bit signal. The output lines of FLB are connected by feedback lines 10 and 11 to condition And's A1 and A3. The later application of a Bit 2...