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Noise Rejection on Data Communication Line

IP.com Disclosure Number: IPCOM000092864D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Athens, AS: AUTHOR [+2]

Abstract

The circuit rejects noise on a data communication line. Utilization of the data received on the communication line is controlled by clock 10. The latter consists of five triggers which provide a count of 0 through 31. Oscillator 12 runs clock 10 at a predetermined frequency. The oscillator 12 pulses are gated through And 14 by the output of clock gating trigger 16. The data is normally gated by a strobe pulse generated by sample pulse driver 18 at 16 time of clock 10 which represents the theoretical mid-point of the data bit. Phase counter 20 senses the data bits and, in conjunction with phase counter control trigger 22 and an output on line 32 from oscillator 12, either advances or retards clock 10 to synchronize clock 10 with the received data.

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Noise Rejection on Data Communication Line

The circuit rejects noise on a data communication line. Utilization of the data received on the communication line is controlled by clock 10. The latter consists of five triggers which provide a count of 0 through 31. Oscillator 12 runs clock 10 at a predetermined frequency. The oscillator 12 pulses are gated through And 14 by the output of clock gating trigger 16. The data is normally gated by a strobe pulse generated by sample pulse driver 18 at 16 time of clock 10 which represents the theoretical mid-point of the data bit. Phase counter 20 senses the data bits and, in conjunction with phase counter control trigger 22 and an output on line 32 from oscillator 12, either advances or retards clock 10 to synchronize clock 10 with the received data.

First transistion trigger 24 performs the noise rejection function for all pulses having a width of less than one-quarter of the theoretical pulse duration for a data bit. When a pulse is received on the line, trigger 24 is set through And 26, since trigger 16 is reset off. The data bit is also combined with some control functions to produce the logic 1 signal which sets trigger 16. Thus, both clock 10 and counter 20 are turned on to count signals from oscillator 12. Counter 20, however, only counts while a valid space bit is being received. A nonspace bit stops counter 20 by deconditioning And 5. At 16 time of clock 10, driver 18 produces an output which is coupled to And 28 an...