Browse Prior Art Database

Memory Block Transfer

IP.com Disclosure Number: IPCOM000092868D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Flaherty, RJ: AUTHOR [+4]

Abstract

The large capacity storage device is adapted to transfer data either one word at a time or in blocks of consecutive addresses. When a single word is to be transferred, the CPU supplies the appropriate address on address bus 3 to register 4. The CPU also supplies a start signal on line 5. The memory then operates conventionally to supply the addressed data on output line 6. The latter is connected to supply the data to a local memory.

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Memory Block Transfer

The large capacity storage device is adapted to transfer data either one word at a time or in blocks of consecutive addresses. When a single word is to be transferred, the CPU supplies the appropriate address on address bus 3 to register 4. The CPU also supplies a start signal on line 5. The memory then operates conventionally to supply the addressed data on output line 6. The latter is connected to supply the data to a local memory.

When a block of words is to be transferred, the CPU supplies a starting address that is stored in register 4 and a final address that is stored in register 7. The CPU also signals the timing and control circuits that a block transfer is to take place. The memory operates on the word designated by register 4 in the conventional way already described. During this memory cycle, the timing signals operate register 4 to advance to the next address. At the end of the first cycle, the timing and control circuit operates the memory through a second cycle at the new address.

During each operation, address comparator circuit 8 compares the address in register 4 with the final address which is held in register 7. When the final address is reached, comparator 8 produces a signal on line 9 that signifies that the block transfer operation is to end.

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