Browse Prior Art Database

First In First Out Buffer Controls

IP.com Disclosure Number: IPCOM000092869D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Dales, MC: AUTHOR [+2]

Abstract

When a plurality of data items are to be stored in a group of storage registers, some hardware can be saved. Such saving is over the conventional type of a stack of addressed buffer registers with input and output address counters or their equivalent, if a group of order bits can be associated with the registers. Buffer registers 1...4 can be selectively coupled to input bus 5 by gates 6. Each register 1...4 also has an output gate 7 which can be activated to pass the data stored in the register to output bus 8. Each register 1...4, has associated with it a full bit trigger 9 which is set when gate 6 of its register 1...4 is activated to load the register. A trigger 9 is reset when the gate 7 is activated to read out the register contents to bus 8.

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First In First Out Buffer Controls

When a plurality of data items are to be stored in a group of storage registers, some hardware can be saved. Such saving is over the conventional type of a stack of addressed buffer registers with input and output address counters or their equivalent, if a group of order bits can be associated with the registers. Buffer registers 1...4 can be selectively coupled to input bus 5 by gates 6.

Each register 1...4 also has an output gate 7 which can be activated to pass the data stored in the register to output bus 8. Each register 1...4, has associated with it a full bit trigger 9 which is set when gate 6 of its register 1...4 is activated to load the register. A trigger 9 is reset when the gate 7 is activated to read out the register contents to bus 8.

The particular order of loading of registers 1...4 is of no importance, so it is assumed that the first empty register is selected to be loaded. Input control 10 receives a signal from each trigger 9 over bus 11 and a load signal from the associated data supply mechanism when data is to be stored. Control 10 then activates a selected gate 6 and sets the trigger 9 for that register.

Control 10 also sets selected ones of a group of order bit triggers 13 to enable the order of loading to be determined. There is trigger 13 for each unique pair of storage registers 1...4, i. e., n!/2! (n-2)! triggers, where n equals number of registers. They indicate register 1 is loaded after register 2,...