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Error Synchronizer

IP.com Disclosure Number: IPCOM000092870D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Boland, LJ: AUTHOR [+3]

Abstract

In data processors having a plurality of storage modules operating in a series interleaved mode, it is desirable to synchronize an error, which can arise at any time during the total storage cycling time of an address reference, with the transmitted address for which the error is detected.

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Error Synchronizer

In data processors having a plurality of storage modules operating in a series interleaved mode, it is desirable to synchronize an error, which can arise at any time during the total storage cycling time of an address reference, with the transmitted address for which the error is detected.

A data processor has instruction unit 1, a plurality of storage modules 2 operating in an interleaved manner, and execution unit 3 receiving data from modules 2 by way of storage bus out SO 4, and transmitting data to modules 2 via storage bus in SI 5. A full cycle of a module 2 takes a plurality of clock cycles of instruction and execution units 1 and 3. The results of error tests on the operation of any one module 2 are available after different numbers of clock cycles from the start of the operation. A storage address is issued by unit 1 on a storage address bus SB 6. The address is tested for validity in an SB test unit 7, whose result is available in that clock cycle and in a storage protect unit 8, whose result is not available until two clock cycles later.

The address is also stored in the top position of a pushdown stack 9 of buffer registers. SB 6 is connected to a memory address register MAR 10 in each module 2. The address is entered into MAR 10 of a selected module. The address, as entered into MAR 10, is tested for validity in MAR test unit 11. Any error signal from unit 19 is available in the next machine cycle after the address is put on SB 6.

At some later time, the fourth clock cycle, the data for entry during a write operation into the addressed module 2, is put on SI 5 by unit 3, and its validity tested by SB test unit 12. Also at some later time, the data for a fetch operation from the addressed module 2 is available on SO 4 and is tested in SO test unit 13.

To indicate the storage address for which an error is detected, pushdown stack 9 is provided with a plurality of error tag positions. The uppermost position of stack 9 is loaded...