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Vernier Timing of Clock Stnchronized Control Signals

IP.com Disclosure Number: IPCOM000092873D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Layden, EC: AUTHOR

Abstract

In data processing systems, generation of clock pulses with accurately timed rise and fall points can be precisely controlled by the use of coarse and fine adjustable delay lines in series. Oscillator 1 drives ring counter 2 of any desired number of stages to provide accurately timed signals on lines 3. Such signals are passed through a chain of interspersed variable delay circuits 4 and amplifiers 5. Each amplifier 5 receives a signal from its input delay 4 and provides both a clock signal output on a line 6 and an input to the succeeding delay 4. By adjustment of the timing controls of delays 4, the sequence of signals on lines 6 can be spaced at any desired time intervals from the minimum of the inherent delay in one amplifier 5 to the interval between output signals of ring 2.

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Vernier Timing of Clock Stnchronized Control Signals

In data processing systems, generation of clock pulses with accurately timed rise and fall points can be precisely controlled by the use of coarse and fine adjustable delay lines in series. Oscillator 1 drives ring counter 2 of any desired number of stages to provide accurately timed signals on lines 3. Such signals are passed through a chain of interspersed variable delay circuits 4 and amplifiers 5. Each amplifier 5 receives a signal from its input delay 4 and provides both a clock signal output on a line 6 and an input to the succeeding delay 4. By adjustment of the timing controls of delays 4, the sequence of signals on lines 6 can be spaced at any desired time intervals from the minimum of the inherent delay in one amplifier 5 to the interval between output signals of ring 2.

For the actual control signals of the processor, the timing of the signals on lines 6 is still too coarse. The length of a clock signal and its rise and fall relative to other signals must be precisely controlled to much finer intervals than can be obtained from lines 6. Such control signals are generated from the signals on lines 6 by circuits comprised of a pair of adjustable delay lines 7, Nor-Nor two- state circuits 8, and amplifiers 9 to drive control lines 10.

Delays 7 have, even at their maximum adjustment, only a very short delay of not more than the time interval between the rise of the signals on two sequential lines 6 and c...