Browse Prior Art Database

Patching a Holographic Read Only Memory

IP.com Disclosure Number: IPCOM000092882D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Krewson, N: AUTHOR [+3]

Abstract

Read-only memories ROM are being increasingly used in data processing systems. One use for an ROM is found in a bulk store device for storing entire systems programs. In the application of a hologram as an ROM, there are encountered problems when re-exposing or correction are desired. This method realizes the desired results.

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Patching a Holographic Read Only Memory

Read-only memories ROM are being increasingly used in data processing systems. One use for an ROM is found in a bulk store device for storing entire systems programs. In the application of a hologram as an ROM, there are encountered problems when re-exposing or correction are desired. This method realizes the desired results.

The device comprises computer CPU 1 including a plurality of standard circuits. An instruction decode circuit IC 3 furnishes information to next address generation circuit AG 5. Read-write core memory CM 7 is addressed by the contents of address register AR 9. CM 7 furnishes information to both IC 3 and AG 5. External to CPU 1 there is a read-only holographic memory HM 11 whose function is to provide instructions to IC 3 over main instruction bus IB 13 and gate the system parallel to HM 11. BHM 17 furnishes information to IC 3 over bus 19 and gate G 21. Storage address register SAR 23 addresses both HM 11 and BHM 17. SAR 23 also furnishes its current address to compare ALU 25 in CPU
1. SAR 23 is responsive to the contents of AG 5. ALU 25 has a second input from BHM 17. The output of ALU 25, indicating a successful compare operation, is applied to selectively operate either G 15 or G 21, thus passing the contents of HM 11 or BHM 17 to IC 3. The output from BHM 17 can be applied to AR 9.

AG 5 constructs the address of the next control word to be accessed. The normal path is through SAR 23 and then to HM 11. The contents of the addressed location are read out into IC 3 by way of IB 13 and G 15. When a change is to be made to the contents of HM 11, BHM 17 is inserted in parallel with HM 11. In this manner, SAR 23 not only addresses a location in HM 11 but also addresses a location in BHM 17. The memory position addressed in BHM 17 contains its own address. This address is transferred to ALU 25 simultaneously with the contents of SAR 23. An equal compare operation indicates that the contents of BHM 17 are to be read into IC 3, rather than the contents of the addressed portion in HM 11.

This selection is accomplished by the appropriate gating of...