Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

OCR Vertical Registration System

IP.com Disclosure Number: IPCOM000092885D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 72K

Publishing Venue

IBM

Related People

Demer, FM: AUTHOR

Abstract

The circuit in drawing A shows a system by which the video data from each vertical scan in an optical character reader can be properly located in storage relative to the data from all other scans.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 40% of the total text.

Page 1 of 4

OCR Vertical Registration System

The circuit in drawing A shows a system by which the video data from each vertical scan in an optical character reader can be properly located in storage relative to the data from all other scans.

The major components used are two four-stage binary counters Prior (Scan) counter 17 and Current (Scan) counter 19. All four stages of each counter are connected to multiple And circuitry by which a comparison of the values standing in each results in either a Hi-Prior, a Hi-Current or an Equal output. The first two of these outputs results in the setting of Hi-Prior and Hi-Current latches 5 and 7 respectively. Once set, these latches remain in the set condition until reset by an Equal output from the comparison unit circuitry 9.

There is a single source of advance pulses for counter 19. The first black bit encountered on any scan sets Video latch 11. All sampling pulses during that scan subsequent to the setting of latch 11 advance counter 19. The latter is reset at the conclusion of each vertical scan.

Counter 17 is subject to advance by any of three sources of advance pulses.
1. On the first scan of a character the Scan 1 latch 13 permits

the advance in synchronism with counter 19.
2. Oscillator pulses advance the counter so long as latch 7 is in

set condition.
3. If latch 5 is set, sampling pulses advance the counter by

successive groups of fourteen pulses, equivalent

to subtracting

one from an earlier value until such time as an equal

condition exists between counters 17 and 19. Counter 17 is

reset only upon completion of the scanning of a character.

The two output pulses of the circuitry are the Storage Matrix Advance pulse 21 and Storage Matrix Down Shift pulse 23. These pulses are operative on the Storage Matrix drive circuitry, not shown, as follows. Pulse 21 is operative during each vertical scan subsequent to the first black bit of the scan. Pulse 21 advances the vertical address of the storage matrix synchronously with the downward progress of the scan so that subsequent black bits in each scan are stored in accordance with their location along the scan. A secondary function of pulse 21 is to determine the vertical address of the first bit under the condition of set for latch 7. Pulse 23 causes the downward shift within the storage matrix of one bit position on each occurrence for all data in one or more scans.

The operation of these circuits is explained in terms of their action during each of ten vertical scans across the letter "A" as in drawing B.

Scan 1. Result, three successive black bits encountered during scan and addressed to rows 1, 2, and 3 of column 1 of the matrix. Latch 11 is set by the first bit. The two following sample pulses time two output pulses 21. On all sample pulses during the scan prior to the first black bit encountered, both counters 17 and 19 had synchronously advanced, assume to a count of ten. The

1

Page 2 of 4

counter 17 advance is permitted by the On condition o...