Browse Prior Art Database

Core Store Addressing

IP.com Disclosure Number: IPCOM000092903D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Harper, LR: AUTHOR

Abstract

This circuit for addressing a magnetic core storage array utilizes the same address drivers for both read and write modes.

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Core Store Addressing

This circuit for addressing a magnetic core storage array utilizes the same address drivers for both read and write modes.

The drive circuit is energized according to either the read or write mode. When it is desired to read, a positive gate signal is applied to terminal 1 causing transistors T2 and T3 to saturate. The resulting lowered potential on line 4 operates to saturate transistors T5 and T6. This accomplishes the read mode. The write mode selection is similar, except that the positive gate signal is applied to terminal 7. This causes transistors T8 and T9 to saturate. The saturation of transistors T10 and T11 follows due to the low potential on line 12.

A row of cores 13 is half-selected according to the address signals supplied to address drivers, four of which, 14...17, are shown. The address drivers pass current in the same direction for both the read and write modes.

Assume that a read mode is selected and the address register, not shown, applies positive gate signals to terminal 18 of driver 14 to saturate transistors T19 and T20. Further, assume that the address register also applies a positive gate signal to terminal 21 of address driver 17 to saturate transistors T22 and T23. In this case, current flows from the positive supply terminal 24 through T5 and T6, diode D25, T22 and T23, diode D26, drive line 27 for row 28, diode D29, T19 and T20, diode D30 and T2 and T3 to terminating resistor 31.

The change between read and write...