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Unijunction Transistor Storage Cell

IP.com Disclosure Number: IPCOM000092917D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Proudman, A: AUTHOR

Abstract

Drawing 1 shows a storage cell comprising a unijunction transistor having bases B1 and B2 connected to bit and word lines VB and VW respectively. Emitter E is connected to potential divider R1 and R2. R1 is connected to word line VW and R2 is connected to a reference potential shown as ground.

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Unijunction Transistor Storage Cell

Drawing 1 shows a storage cell comprising a unijunction transistor having bases B1 and B2 connected to bit and word lines VB and VW respectively. Emitter E is connected to potential divider R1 and R2. R1 is connected to word line VW and R2 is connected to a reference potential shown as ground.

To interrogate the cell, the potential on VW is changed. A signal on VB appears in accordance with whether the cell is storing a 0 or 1. If a negative going voltage pulse is employed on VB, the state of the cell must not be changed. To write information, the potential on VW is decreased. The potential on VB decreased or increased in accordance as to whether it is desired to store a 1 or 0.

The performance of the cell is shown in drawing 2. This shows voltages to be applied to VW and VB to store a 0 or 1. As the word potential is decreased, the sensitivity of the cell to a change in state increases. The values of R1 and R2 are chosen so that the mean of the turnon and turnoff potentials on VB remains constant with varying VW potential. In a matrix of storage cells, each cell can have associated with it an individual potential divider. Also, all the cells in a particular word can be connected to a common potential divider.

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