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Gated Transmission Line Receiver

IP.com Disclosure Number: IPCOM000092919D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Low, PY: AUTHOR [+4]

Abstract

This circuit provides gated input to a transmission line receiver. Transistors T1 and T2 must be biased nonconductive in order to render transistors T3 and T4 conductive. This requires that there be a high-level input signal at both the data and gate inputs. Whenthere is a low-level signal on either the data or the gate input, the voltage at node A is maintained at a low level by conduction through either T1 or T2.

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Gated Transmission Line Receiver

This circuit provides gated input to a transmission line receiver. Transistors T1 and T2 must be biased nonconductive in order to render transistors T3 and T4 conductive. This requires that there be a high-level input signal at both the data and gate inputs. Whenthere is a low-level signal on either the data or the gate input, the voltage at node A is maintained at a low level by conduction through either T1 or T2.

The low-level voltage at A biases T3 and T4 nonconductive to maintain the output of the circuit high. However, when there is a high-level input signal at both the data and gate inputs, neither T1 or T2 can conduct and therefore the voltage at A is at a high level. This high level biases T3 and T4 conductive so that the output of the circuit is low.

Resistor R2 minimizes interaction between the data and gate inputs. This interaction can also be minimized by employing transistors with high reverse beta characteristics for T1 and T2.

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