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Current Switching Latch

IP.com Disclosure Number: IPCOM000092922D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Muhlfeld, HP: AUTHOR

Abstract

This is a latch employing current switching technology. With either transistor T1 or T2 conducting, transistor T3 is biased off. Likewise, with transistor T5 conducting, transistor T6 is biased off. With both T3 and T6 off, transistor T7 is held on by the + V power supply. Therefore, T7 provides a low-impedance path between the + V power supply and the output thus maintaining the output at a positive potential that keeps T5 on.

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Current Switching Latch

This is a latch employing current switching technology. With either transistor T1 or T2 conducting, transistor T3 is biased off. Likewise, with transistor T5 conducting, transistor T6 is biased off. With both T3 and T6 off, transistor T7 is held on by the + V power supply. Therefore, T7 provides a low-impedance path between the + V power supply and the output thus maintaining the output at a positive potential that keeps T5 on.

To latch the circuit, T1 and T2 must be simultaneously biased off by the set and information inputs respectively. This turns T3 on which then turns T7 off. With T7 off, the output voltage goes to some negative potential determined by the - V power supply. This drop in the output voltage turns T5 off so that T6 is turned on to maintain T7 off whether T1 and T2 are conducting or not. This is the latched condition of the circuit.

To reset the circuit, T4 is rendered conductive by signals on the reset input. These bias, T6 nonconductive, which action allows T7 to be rendered conductive by the + V power supply.

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