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Self Correcting Time Interval Storage Device

IP.com Disclosure Number: IPCOM000092928D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR [+2]

Abstract

This circuit divides the time between regularly occurring index signals into a number of equally spaced intervals.

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Self Correcting Time Interval Storage Device

This circuit divides the time between regularly occurring index signals into a number of equally spaced intervals.

Counter 10 has one more state than the number of intervals n desired and is stepped through all these states by the output of single-shot 12. The latter is controlled by timing circuit 14. In circuit 14, capacitor C1 is charged by source V1 through resistor R2.

Eventually the voltage on C1 exceeds the potential on capacitor C2. When this occurs, transistor T4 conducts biasing T5 conductive. The output of T5 then causes single-shot 12 to produce an output signal. This signal goes to counter 10 to step it from one position to another. The output of single-shot 12 is also fed back into transistor T3. Transistor T3, previously nonconductive, conducts and discharges C1 so that T4 is biased nonconductive.

At the end of the output signal from single-shot 12, T3 is again biased nonconductive and the voltage from V1 starts charging C1 once more. As C1 charges, the potential across it eventually exceeds the potential across C2. This renders T4 conductive again thus starting another cycle which results in another output pulse from single-shot 12. Therefore, counter 10 is stepped through all its positions, one step at a time, by the regularly occurring output signals from single-shot 12 until the last state, or the n + 1 state, of single-shot 12 is reached.

When the last or unused state n + 1 of single-shot 12, is reached, decoder 16 sends a signal to And 18. If the pulses are properly spaced, this occurs simultaneously with the arrival of the regularly occurring index signal at the set input of latch 20. The output of And 18 then resets counter 10 to theta position which then unlatches latch 20 by sending a signal to the reset position of such latch. However, if the index signal and the n + 1 state of counter 10 do not occur simulta...