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An Integration Approach for Ge

IP.com Disclosure Number: IPCOM000092930D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Light, TB: AUTHOR [+2]

Abstract

These several methods are for fabricating semiconductor devices in a planar regime. Such methods obviate the current difficulties of obtaining smooth surfaces. They permit obtaining large diameter substrates and avoid the problem of growing two epitaxial layers of germanium on semi-insulating gallium arsenide. The basic method consists of: 1. In drawing 1, growing a layer of germanium on a thin germanium substrate by the tetrahalide reduction of GeCl(4). Both layers are of a desired resistivity level and conductivity type, 2. In drawing 2, depositing semi-insulating gallium arsenide on the underside of the substrate by sputtering, flash evaporation or other suitable low temperature technique, 3. In drawing 3, etching islands in the Ge layers down to the gallium arsenide, and 4.

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An Integration Approach for Ge

These several methods are for fabricating semiconductor devices in a planar regime. Such methods obviate the current difficulties of obtaining smooth surfaces. They permit obtaining large diameter substrates and avoid the problem of growing two epitaxial layers of germanium on semi-insulating gallium arsenide. The basic method consists of:
1. In drawing 1, growing a layer of germanium on a thin

germanium substrate by the tetrahalide reduction of GeCl(4).

Both layers are of a desired resistivity level and

conductivity type,
2. In drawing 2, depositing semi-insulating gallium arsenide on

the underside of the substrate by sputtering, flash

evaporation or other suitable low temperature technique,
3. In drawing 3, etching islands in the Ge layers down to the

gallium arsenide, and
4. In drawing 4, backfilling the spaces between islands with

either semi-insulating gallium arsenide or a layer of suitable

oxide such as SiO(2) or Al(2)O(3) followed by a backfilling

with semi-insulating GaAs. The backfilled surface is then

polished to provide a planar surface in which the germanium is

now imbedded.

Alternatively in step 2, the germanium substrate can be thinned down after the epitaxial deposition of germanium to a thickness of 0.5-1 mil and then semi- insulating gallium arsenide is deposited on the substrate underside.

Another alternative, after step 1, is to take the germanium-on-germanium wafer and fabricate and interconnect on it, as in dra...