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Browse Prior Art Database

Isolation Technique for Ge Integrated Circuits

IP.com Disclosure Number: IPCOM000092931D
Original Publication Date: 1967-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Light, TB: AUTHOR [+3]

Abstract

This technique is for isolating islands of germanium or other semiconductor material upon which devices such as transistors can be formed. The method shown in the drawings consists of the steps of: 1. Growing or diffusing-in a p/+/ layer of germanium on an n/-/ germanium substrate and then epitaxially depositing a layer of p-type germanium on the p/+/ layer, 2. Using photolithography and SiO(2) masking, the p/+/, n/-/ and p-type layers are etched down to the n/-/ gerrnanium substrate along desired lines to form islands of germanium on the n/-/ substrate, 3. Etching around the periphery to etch back slightly the SiO(2) layer on top of each island, 4. Flash-evaporating chromium doped semi-insulating gallium arsenide to fill the spaces between the islands and to cover the surface of the islands, 5.

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Isolation Technique for Ge Integrated Circuits

This technique is for isolating islands of germanium or other semiconductor material upon which devices such as transistors can be formed. The method shown in the drawings consists of the steps of:
1. Growing or diffusing-in a p/+/ layer of germanium on an n/-/

germanium substrate and then epitaxially depositing a layer

of p-type germanium on the p/+/ layer,
2. Using photolithography and SiO(2) masking, the p/+/, n/-/ and

p-type layers are etched down to the n/-/ gerrnanium substrate

along desired lines to form islands of germanium on the

n/-/ substrate,
3. Etching around the periphery to etch back slightly the SiO(2)

layer on top of each island,
4. Flash-evaporating chromium doped semi-insulating gallium

arsenide to fill the spaces between the islands and to cover

the surface of the islands,
5. Lapping the surface of the gallium arsenide to make it planar,

and
6. Polishing the surface chemically using an NaOCl polishing

technique described in "Room Temperature Polishing of Ge

and GaAs" by A. Reisman and R. L. Rohr, published in The

Journal of The Electrochemical Society, Vol. III, No. 12,

Page 1425, December, 1964, until the gallium arsenide surface

is brought level with the germanium surface.

The SiO(2) layer is then removed and devices are fabricated in the islands by well-known diffusion techniques. By biasing the substrate, the undersides of the germanium islands are isolated from each other in the n/-/ region....