Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Speed Parallel Counter

IP.com Disclosure Number: IPCOM000092978D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Connelly, DP: AUTHOR [+2]

Abstract

The high-speed, parallel counter in drawing 1 counts the number of input lines, at the left-hand side, which are in an excited state. The counter is to detect when more than fifteen of the input lines are in an excited state. In addition, by using a clock signal, one group of input lines can be counted in one interval and their sum added to the count from another group of input lines in the next interval.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

High Speed Parallel Counter

The high-speed, parallel counter in drawing 1 counts the number of input lines, at the left-hand side, which are in an excited state. The counter is to detect when more than fifteen of the input lines are in an excited state. In addition, by using a clock signal, one group of input lines can be counted in one interval and their sum added to the count from another group of input lines in the next interval.

The input to the counter consists of twenty-seven lines each of which may or may not be in an excited state. The twenty-seven input lines are divided into three groups of nine. Each group is further divided into two sets of four plus one. Each set of four lines is monitored by a four-bit counter. Four-bit counters 20...25 each count the number of lines in a set of four which are in an excited state. The outputs from the four-bit counters are fed to three 5 by 5 adder matrices.

In drawing 2, a three by four example of an adder matrix is shown. The adder matrix is made up of And's each of which has two inputs. Each And is assigned the representation of a particular combination of addend inputs. For example, And 26 represents the combination of addens 0 and 3. Therefore, if And 26 has an output, the sum of the adder matrix is 3. The common output conditions from And's in the matrix having the same output are collected in Or's such as Or 28. The latter detects the sum three and has an output signal if it receives a signal from And 26, And 30 or And 32. And 30 represents the combination of addends 1 and 2 while And 32 represents the combination of addends 2 and 1.

In drawing 1, the 5 by 5 adder matrices 34, 36, and 38 add together the outputs from two of the four-bit counters. Thus the output of each adder matrix indicates the number of lines in a set of eight which are in an excited state. Adders 40, 42, and 44 increment by 1 the output from adder matrices 34, 36 and 38, respectively. This occurs if the additional line applied to the adders 40, 42, and 44 is in an excited state. Thus the output from the adders 40, 42, and 44 indicates the number of lines in a set of nine which are in an excited state.

The counts for two of the sets of nine are added together in...