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Reversible Binary Counter with Overflow Prevention and Preset Features

IP.com Disclosure Number: IPCOM000092991D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Lear, JR: AUTHOR

Abstract

This binary counter, which counts up or down one count per input pulse, which can be preset to any desired value, and which blocks an input pulse that would cause an overflow, uses Nand logic.

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Reversible Binary Counter with Overflow Prevention and Preset Features

This binary counter, which counts up or down one count per input pulse, which can be preset to any desired value, and which blocks an input pulse that would cause an overflow, uses Nand logic.

The counter contains two flip-flop F-F registers, rows B and G, per bit, ripple- type carry propagation logic, and control logic. Each F-F comprises two Nand gates. When the counter is idle, the upper F-F register row B, follows the lower master register, row G, so that A2 always is the same as A1, B2 the same as B1, etc.

The carry propagation logic has inputs of the current counter value from row B and a counting direction signal. The logic gates in rows C and D determine whether or not the F-F's in row G are to be changed by the next count pulse. The output from the highest stage N is used as an input to the control logic to block or pass the count pulse and provide overflow prevention.

The operation of the counter is as follows, assuming that the set line is a logical 1:
1. The direction signal is set to either a logical 1 for

incrementing or a logical 0 for decrementing if it is not

already in the correct state.
2. The lock signal is set to a logical 1 so that the gates in

row A cannot set or reset the F-F's in row B.
3. After a time delay, ripple time, the pulse signal is

driven to the 1 state.
4. If this pulse does not cause an overflow, it passes to the

gates in row F which change the F-F's in row...