Browse Prior Art Database

Binary to Video Converter

IP.com Disclosure Number: IPCOM000092996D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Handloff, LE: AUTHOR

Abstract

The apparatus of drawings 1 and 2 converts stored binary data into nary video-compatible signals for transmission to video displays.

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Binary to Video Converter

The apparatus of drawings 1 and 2 converts stored binary data into nary video-compatible signals for transmission to video displays.

The binary data shown in 3C is utilized to represent the analog video information shown in 3A. Various strings of such binary data and a clock signal are received in parallel by individual preamps 10. The horizontal flyback signals of the binary video data are synchronized with the clock signals. The vertical flyback signals for each string of video data are independent of those for the others. The clock signal is decoded by clock counter logic 11 and formed into various timing pulses by clock signal generator 12. The timing pulses are supplied on various lines to a blanking gate generation logic circuit 22 for each display unit.

The first timing pulse A occurs after a horizontal line to operate test gate latch 13, as shown by 4A, to thus inhibit And's 14...16 and block the flow of any data of 4B to the display unit. Timing pulse C of 4C is then applied to the reset input of VFB latch 17 to insure that the latch is off. Timing pulse D then opens And 18 to detect any binary vertical flyback signal in the video data B.

In the event no vertical flyback signal is present to be gated by And 18, VFB latch 17 remains off, inhibiting gating of any further signals by And 16. Then, timing pulse E1 is applied to the set input of HFB latch 19 to operate the latch. The output from HFB latch 19 in 4E turns off latch 13. The output of the latter, 4A, is supplied to And' s 14...16. At the same time, the output from HFB latch 19 also is supplied directly to And 15. This, in combination with the Not Test Gate output 4A, enables the And to gate the HFB signal of the video data 4B, via Or 20, to the sync input of mixer 21. This signal comprises the blanking gate signal of 4E.

The sync input overri...