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Linkage Tags Between Matching Storage Addresses

IP.com Disclosure Number: IPCOM000092997D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+6]

Abstract

In high-performance computing systems having a plurality of storage modules, operated in overlapped machine cycles, and also having a number of buffer registers in which access requests for busy storage modules can be temporarily stored, some time is saved and logical correctness is preserved. Such occur if successive references to the same storage address can be chained together. Storage control unit 1 has Storage Address Bus AB 2 which is supplied with the storage address to be accessed. Storage 3 is composed of a plurality of modules containing storage addresses distributed in sequence among the modules. If a storage address on AB 2 corresponds to an address in a nonbusy module, the address is accepted to start a storage cycle in the module and is entered into an Accept Stack AS 4.

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Linkage Tags Between Matching Storage Addresses

In high-performance computing systems having a plurality of storage modules, operated in overlapped machine cycles, and also having a number of buffer registers in which access requests for busy storage modules can be temporarily stored, some time is saved and logical correctness is preserved. Such occur if successive references to the same storage address can be chained together. Storage control unit 1 has Storage Address Bus AB 2 which is supplied with the storage address to be accessed. Storage 3 is composed of a plurality of modules containing storage addresses distributed in sequence among the modules. If a storage address on AB 2 corresponds to an address in a nonbusy module, the address is accepted to start a storage cycle in the module and is entered into an Accept Stack AS 4.

The latter is a pushdown stack with registers for five addresses.

AS 4 contains a control section to control the timing of data transfer from Storage Bus In B1 5 to the addressed module or to the Storage Bus Out B0 6 from the addressed module. The control section also sends out busy signals for the storage modules.

Any address on AB 2 which cannot be accepted by a storage module is buffered in Request Stack RS 7 until the module is not busy, at which time it is reissued on the AB 2. Two or more requests for access to the same module are reissued on a first-in, first-out basis. Normally a storage acces s request for a store operationis automatically rejected into Storage Address AR 8 until the data to be stored is available in an associated Storage Data Buffer DB 9. At such time, the address is reissued on AB 2 into AS 4, or into RS 7, depending upon the busy status of the required storage module.

Address Comparator 10 is connected to AB 2, AS 4, RS 7, and AR 8, to re...