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Selective Gating of Exception Tags

IP.com Disclosure Number: IPCOM000092998D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Adler, JD: AUTHOR [+2]

Abstract

In early data processors, the Translate and Test TRT instruction is performed by first fetching a byte of an argument word. The data in that byte is used together with a table base address specified in the TRT instruction to generate the address of a byte in storage. That storage byte is inspected and execution of the instruction is terminated if the inspected table byte is not zero. In recent processors, the execution of the TRT instruction is speeded up. This is effected by extensive overlapping of the operations of fetching argument words and fetching table bytes from storage and buffering the fetched data. The objective is to approach the limit of testing one table byte on each cycle of the processor.

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Selective Gating of Exception Tags

In early data processors, the Translate and Test TRT instruction is performed by first fetching a byte of an argument word. The data in that byte is used together with a table base address specified in the TRT instruction to generate the address of a byte in storage. That storage byte is inspected and execution of the instruction is terminated if the inspected table byte is not zero. In recent processors, the execution of the TRT instruction is speeded up. This is effected by extensive overlapping of the operations of fetching argument words and fetching table bytes from storage and buffering the fetched data. The objective is to approach the limit of testing one table byte on each cycle of the processor.

The overlapping of fetches starts with a fetch request from instruction decoder 1 for the double word from main store 2. The word address within store 2 is determined in address generator 3 as the address of the double word, eight bytes, containing the starting byte of the argument words. This fetch is followed on the next cycle by a second fetch request for the next double word of the argument from the succeeding address of store 2. When the first argument word is returned from store 2, it is directed into an A register 4 for processing. The second argument word from store 2 is directed into one of a stack 5 of data buffers to be available for transfer into Reg 4. Decoder 1 has also issued the first instruction of a series defining the execution of a TRT instruction to one of a stack 6 of instruction buffers. Instruction control 7 decodes the instruction from a buffer 6 and starts execution of the instruction as soon as the first argument word is received in Reg 4. The first byte of the argument word in Reg 4 is then gated out to the processors instruction unit where it is combined in generator 3 with the table base address given in the TRT instruction.

The TRT instruction is held in decoder 1 to enable generator 3 to use its data to generate the address in store 2 of the first table byte to be inspected. A fetch request is issued to store 2 for the word containing this table byte. The fetch request for this word specifies that the word is to be returned to one buffer 5. Decoder 1, when it is sues the fetch request, also sends an instruction to buffers 6 indicating the buffer 5 receiving the table word and also designating the byte which is to be inspected. On the cycle immediately following the transmission of the first argument byte from Reg 4, the second argument byte is gated out to the instruction unit. The latter starts another address generation operation and issues a fetch request for a second table word to be returned to a second buffer of stack 5 and issues a second instruction to buffers 6. This argument byte transmission, table...