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Fast Latched Circuit for Sum Formation

IP.com Disclosure Number: IPCOM000093002D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Wade, RM: AUTHOR

Abstract

In a long carry propagate adder divided into sections with carry propagate circuits between the sections, the circuit with the most logic levels, and hence the one requiring the most time, is the carry circuit including a sum output of one section and the carry generate circuits of a preceding section. Any reduction in the number of logic levels in this path results in a corresponding speedup in the overall timing of the adder.

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Fast Latched Circuit for Sum Formation

In a long carry propagate adder divided into sections with carry propagate circuits between the sections, the circuit with the most logic levels, and hence the one requiring the most time, is the carry circuit including a sum output of one section and the carry generate circuits of a preceding section. Any reduction in the number of logic levels in this path results in a corresponding speedup in the overall timing of the adder.

In the drawing, there is one order of a carry propagate adder in which there is only one level of logic between the carry in signal Cin to the section and the sum signal S corresponding to that carry in signal combined with the entries into the order. In this order, the nth, the incoming bits An and Bn on lines 1 and 2 are combined in Exclusive-Or 3 to generate a half-sum HS signal on a line 4, and a not half-sum signal -HS on line 5. The local carry signal CL for this nth order on line 6 and the not carry signal -CL on line 7 are generated on Or 8 as the Boolean sum of the carry generate signal C(n-1) of the next lower order on line 9, the carry propagate signal P(n-1) and the carry generate signal C(n-2) of the next two lower orders on line 10, the P(n-1), P(n-2) and C(n-3) signals on a line 11, etc., to the C(n-k) of the lowest order of the section. A local section propagate signal P(L)on line 12 and a not local propagate signal -P(L) on line 13 are generated in And 14 from the propagate signal P(n-1) on line 15, P(n-2) on line 16, P(n-3) on line 17, etc., to the lowest order of the adder section. The carry and propagate signals can be replaced by the corresponding functions for the zero signal, i. e., by the carry zero and propagate zero signals. Use of such zero signals requires minor c...