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Serrated Flattened Pad for Backdown Mounted Chip Devices

IP.com Disclosure Number: IPCOM000093057D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hayunga, CP: AUTHOR [+2]

Abstract

Semiconductive chip devices are backside mounted to enlarged, flattened, solder-coated pads on insulating substrates. Prior to joining, flux is applied to the pad resulting in a thin-film buildup as shown in A. Because of the large area of the interface, the chip floats on the flux, disrupting the alignment of the chip contact balls to their straps and leading to possible shorting out. Voids can also appear between chip and pad resulting in poor thermal conductivity. To correct this condition, the solder-coated pad is serrated, as shown in B and C, reducing the interface. These serrations allow localized flux to escape along with its vapors. Chip movement is curtailed and strap shorting is no longer a problem.

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Serrated Flattened Pad for Backdown Mounted Chip Devices

Semiconductive chip devices are backside mounted to enlarged, flattened, solder-coated pads on insulating substrates. Prior to joining, flux is applied to the pad resulting in a thin-film buildup as shown in A. Because of the large area of the interface, the chip floats on the flux, disrupting the alignment of the chip contact balls to their straps and leading to possible shorting out. Voids can also appear between chip and pad resulting in poor thermal conductivity. To correct this condition, the solder-coated pad is serrated, as shown in B and C, reducing the interface. These serrations allow localized flux to escape along with its vapors. Chip movement is curtailed and strap shorting is no longer a problem.

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